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xp075287

10Gbit/s0.18μm CMOS1: 4 tap IC

Degree of 187mV, the signal jitter shown in Figure 8 , the clock jitter rms as 1.1ps. Thus the scores received data eye jitter is small , the rms jitter is only 4ps. After testing , the clock module can be completed in 2 minutes 9GHz frequency band work,[link widoczny dla zalogowanych], the duty cycle is 50.4%. Clock output amplitude of 89mV. The clock module can be used in theory, 18Gbit / s data rate sub- half rate clock circuitry. Ek Mexico mI feet ~ mutecap2lOet ~ Alexandra Ang C_ Man 2bj ear and then i take --------- Figure 82 one hundred and eleven divided by the chip clock jitter distribution of the test , the circuit up to the 13.5Gbit / s on Complete the 4-way tap . Table 1 Characteristics of the chip , the output of 3.375Gbit / s data eye shown in Figure 9. Table 2 shows the performance of the circuit chip features comparison Table 1 Figure 93.375Gbit / s single-ended output data eye diagram 2 Circuit Comparison at Fort One wall ! obstruct Gen dust ! 422838755.9I82352OI54. I4 Conclusion In this paper, TSMC0.18mCMOS process design of the chip Gigabit Ethernet tap , and through the silicon wafer testing and validation at the end of which 1:4 tap high-speed circuit, the circuit can operate at the highest 13.5Gbit / s, the chip can be used for Gigabit Ethernet 10GBASE-R, 10GBASE. W series and SDH-64 (SONET-192) and other systems. Work in the 10Gbit / s , the chip power 500mw, after a 4-way tap data jitter 4ps, single-ended output signal range of 228mV.